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CBTL06122
High-performance DisplayPort/PCIe Gen2 hex display multiplexer
Rev. 02 -- 16 April 2009 Product data sheet
1. General description
The CBTL06122 is a six-channel (`hex') multiplexer for DisplayPort and PCI Express Gen2 applications. It provides four differential channels capable of switching or multiplexing (bidirectional and AC-coupled) PCI Express Gen2 or DisplayPort signals, using high-bandwidth pass-gate technology. Additionally, it provides for switching/multiplexing of the Hot Plug Detect signal as well as the AUX or DDC (Direct Display Control) signals, for a total of six channels. The CBTL06122 is designed for high-performance PCI Express Gen2 and DisplayPort applications. The device is available in two different pinouts (A and B, orderable as separate part numbers) to suit different motherboard layout requirements. The typical application of CBTL06122 is on motherboards, docking stations or add-in cards where the graphics and I/O system controller chip utilizes I/O pins that are configurable for either PCI Express or DisplayPort operation. The hex display MUX can be used in such applications to route the signal from the controller chip to either a physical DisplayPort connector or a PCI Express connector using its 1 : 2 multiplexer topology. The controller chip selects which path to use by setting a select signal (which can be latched) HIGH or LOW. Optionally, the hex MUX device can be used in conjunction with an HDMI/DVI level shifter device (PTN3300A, PTN3300B or PTN3301) to allow for DisplayPort as well as HDMI/DVI connectivity.
NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
MULTI-MODE DISPLAY SOURCE
4
CBTL06122
4
DP PEG
DisplayPort connector
HPD
AUX
4
docking connector DisplayPort REPEATER
DisplayPort connector
002aad649
Fig 1.
Intended usage 1: DisplayPort docking solution for mobile platform
MULTI-MODE DISPLAY SOURCE
CBTL06122
HDMI/DVI
4 4
PTN3300A/B or PTN3301
HDMI/DVI connector
PEG
HPD
DDC
4
docking connector dock PTN3300A/B or PTN3301
HDMI/DVI connector
002aad650
Fig 2.
Intended usage 2: HDMI/DVI docking solution for mobile platform
CBTL06122_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
2 of 19
NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
DDC MULTI-MODE DISPLAY SOURCE DP/HDMI/ DVI/PEG
4
CBTL06122
4
PTN3300A/B or PTN3301
DP/ HDMI/ DVI connector
PEG HPD/PEG RX
AUX/PEG RX
4
x16 PEG connector
002aad651
Fig 3.
Intended usage 3: Digital display + external graphics solution for desktop platform
2. Features
I 1 : 2 multiplexing of DisplayPort (v1.1 - 2.7 Gbit/s) or PCI Express (Gen2 - 5.0 Gbit/s) signals N 4 high-speed differential channels N 1 channel for AUX differential signals or DDC clock and data N 1 channel for HPD I High-bandwidth analog pass-gate technology I Very low intra-pair differential skew (< 5 ps) I Very low inter-pair skew (< 180 ps) I All path delays matched including between RX1- to X- and RX1+ to X+ I Switch/MUX position select with latch function I Shutdown mode CMOS input I Shutdown mode minimizes power consumption while switching all channels off I Very low operation current of 0.2 mA typ I Very low shutdown current of < 10 A I Standby mode minimizes power consumption while switching all channels off I Single 3.3 V power supply I ESD 4 kV HBM, 1 kV CDM I Two pinouts (A and B) available as separate ordering part numbers I Available in 11 mm x 5 mm HWQFN56R package
CBTL06122_2
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Product data sheet
Rev. 02 -- 16 April 2009
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NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
3. Applications
I Motherboard applications requiring DisplayPort and PCI Express Gen 2 switching/multiplexing I Docking stations I Notebook computers I Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board connectors
4. Ordering information
Table 1. Ordering information Package Name CBTL06122AHF[1][2] CBTL06122BHF[1][2]
[1] [2] [3]
Type number
Description plastic thermal enhanced very very thin quad flat package; no leads; 56 terminals; resin based; body 11 x 5 x 0.7 mm[3]
Version SOT1033-1
HWQFN56R
The A and B suffix in the part number correspond to the A and B pinouts, respectively (see Figure 5 and Figure 6). HF is the package designator for the HWQFN package. Total height after printed-circuit board mounting = 0.8 mm (max.).
CBTL06122_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
4 of 19
NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
5. Functional diagram
MULTI-MODE DISPLAY SOURCE
SEL LE_N XSD MUX LOGIC
CBTL06122
PCIe PHY ELECTRICAL PCIe output buffer
AC-coupled differential pair DATA LANE
IN_0+ IN_0-
D0+ D0-
TX
TX0+ TX0- AC-coupled differential pair DATA LANE D1+ D1-
PCIe output buffer
IN_1+ IN_1-
TX
TX1+ TX1- AC-coupled differential pair DATA LANE D2+ D2-
PCIe output buffer
IN_2+ IN_2-
TX
TX2+ TX2- AC-coupled differential pair DATA LANE D3+ D3-
PCIe output buffer
IN_3+ IN_3-
TX
TX3+ TX3- HPD
PCIe input buffer
X+ RX1+ X- to RX1- path matches X+ to RX1+ path
RX X-
SPARE RX1-
PCIe input buffer AUX DATA RX
AUX+ OUT+ OUT- RX0+ RX0- AUX-
TX PEG CONNECTOR OR DOCKING CONNECTOR
002aad652
Fig 4.
CBTL06122_2
Functional diagram
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
DP CONNECTOR 5 of 19
NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
6. Pinning information
6.1 Pinning
TX0+ TX1+ TX0- TX1- GND GND GND GND 49 XSD XSD 50 VDD VDD D0+ D1+ 52 D0- D1- 51
terminal 1 index area GND IN_0+ IN_0- IN_1+ IN_1- VDD IN_2+ IN_2- IN_3+ IN_3- GND OUT+ OUT- X+ X- GND VDD SEL LE_N GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
terminal 1 index area 48 47 46 45 44 43 42 41 40 39 GND TX2+ TX2- TX3+ TX3- D0+ D0- D1+ D1- D2+ D2- D3+ D3- GND VDD RX0+ RX0- RX1+ RX1- GND GND SEL LE_N IN_0+ IN_0- VDD IN_1+ IN_1- IN_2+ IN_2- GND IN_3+ IN_3- OUT+ OUT- GND VDD X+ X- GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
56
55
54
53
52
51
50
49
56
55
54
53
48 47 46 45 44 43 42 41 40 39
GND D2+ D2- D3+ D3- TX0+ TX0- TX1+ TX1- TX2+ TX2- TX3+ TX3- GND VDD AUX+ AUX- HPD SPARE GND
CBTL06122AHF
A pinout
38 37 36 35 34 33 32 31 30 29
CBTL06122BHF
B pinout
38 37 36 35 34 33 32 31 30 29
21
22
23
24
25
26
27
28
21
22
23
24
25
26
27 VDD
VDD
AUX-
VDD
VDD
RX1-
AUX+
RX1+
RX0-
GND
GND
GND
RX0+
SPARE
Transparent top view
002aad653
Transparent top view
Fig 5.
Pin configuration for HWQFN56R, A pinout
Fig 6.
Pin configuration for HWQFN56R, B pinout
CBTL06122_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
GND
002aad654
HPD
28
6 of 19
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CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
6.2 Pin description
Table 2. Symbol SEL LE_N XSD Pin description Pin Pinout A Pinout B 18 19 50 2 3 50 3.3 V low-voltage CMOS single-ended input 3.3 V low-voltage CMOS single-ended input 3.3 V low-voltage CMOS single-ended input SEL controls the MUX through a flow-through latch. The latch gate is controlled by LE_N. Optional shutdown pin. Should be driven HIGH or connected to VDD for normal operation. When LOW, all paths are switched off (non-conducting) and supply current consumption is minimized. Differential input from PCIe connector or device. RX0+ makes a differential pair with RX0-. RX0+ is passed through to the OUT+ pin when SEL = 0. Differential input from PCIe connector or device. RX0- makes a differential pair with RX0+. RX0- is passed through to the OUT- pin when SEL = 0. Differential input from PCIe connector or device. RX1+ makes a differential pair with RX1-. RX1+ is passed through to the X+ pin when SEL = 0. Differential input from PCIe connector or device. RX1- makes a differential pair with RX1+. RX1- is passed through to the X- pin on a path that matches the RX1+ to X+ path. Differential input from display source PCIe outputs. IN_0+ makes a differential pair with IN_0-. Differential input from display source PCIe outputs. IN_0- makes a differential pair with IN_0+. Differential input from display source PCIe outputs. IN_1+ makes a differential pair with IN_1-. Differential input from display source PCIe outputs. IN_1- makes a differential pair with IN_1+. Differential input from display source PCIe outputs. IN_2+ makes a differential pair with IN_2-. Differential input from display source PCIe outputs. IN_2- makes a differential pair with IN_2+. Differential input from display source PCIe outputs. IN_3+ makes a differential pair with IN_3-. Differential input from display source PCIe outputs. IN_3- makes a differential pair with IN_3+. Low frequency, 0 V to 5 V/3.3 V (nominal) input signal. This signal comes from the HDMI/DP connector. Voltage HIGH indicates a `plugged' state; voltage LOW indicates `unplugged'. Low frequency, 0 V to 5 V/3.3 V (nominal) input signal. This signal comes from the HDMI/DP connector. Analog `pass-through' output corresponding to RX1+. Type Description
RX0+
33
26
differential input
RX0-
32
25
differential input
RX1+
31
24
differential input
RX1-
30
23
differential input
IN_0+ IN_0- IN_1+ IN_1- IN_2+ IN_2- IN_3+ IN_3- HPD
2 3 4 5 7 8 9 10 24
4 5 7 8 9 10 12 13 31
differential input differential input differential input differential input differential input differential input differential input differential input high-voltage single-ended input
X+
14
18
(SEL = HIGH); HPD: high-voltage single-ended input (SEL = LOW); X+: pass-through output
CBTL06122_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
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CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
Table 2. Symbol X-
Pin description ...continued Pin Pinout A Pinout B 15 19 pass-through output from RX1- input X- is an analog `pass-through' output corresponding to the RX1- input. The path from RX1- to X- is matched with the path from RX1+ to X+. X+ and X- form a differential pair when the pass-through MUX mode is selected. Analog `pass-through' output 1 corresponding to IN_0+ and IN_0-, when SEL = 1. Analog `pass-through' output 1 corresponding to IN_1+ and IN_1-, when SEL = 1. Analog `pass-through' output 1 corresponding to IN_2+ and IN_2-, when SEL = 1. Analog `pass-through' output 1 corresponding to IN_3+ and IN_3-, when SEL = 1. Analog `pass-through' output 2 corresponding to IN_0+ and IN_0-, when SEL = 0. Analog `pass-through' output 2 corresponding to IN_1+ and IN_1-, when SEL = 0. Analog `pass-through' output 2 corresponding to IN_2+ and IN_2-, when SEL = 0. Analog `pass-through' output 2 corresponding to IN_3+ and IN_3-, when SEL = 0. Supply voltage (3.3 V 10 %). Type Description
D0+ D0- D1+ D1- D2+ D2- D3+ D3- TX0+ TX0- TX1+ TX1- TX2+ TX2- TX3+ TX3- VDD
43 42 41 40 39 38 37 36 54 53 52 51 47 46 45 44
54 53 52 51 47 46 45 44 43 42 41 40 39 38 37 36
pass-through output 1, option 1 pass-through output 2, option 1 pass-through output 3, option 1 pass-through output 4, option 1 pass-through output 1, option 2 pass-through output 2, option 2 pass-through output 3, option 2 pass-through output 4, option 2
6, 17, 22, 6, 17, 22, 3.3 V supply 27, 34, 27, 34, 55 55 26 25 12 13 1, 11, 16, 20, 21, 28, 29, 35, 48, 49, 56 23 33 32 14 15 differential input differential input differential input differential input
AUX+ AUX- OUT+ OUT- GND[1]
High-speed differential pair for AUX signals. High-speed differential pair for PCIe RX0+ signal. High-speed differential pair for PCIe RX0- signal. Ground.
1, 11, 16, supply ground 20, 21, 28, 29, 35, 48, 49, 56 30 single-ended input
SPARE
Spare channel for general-purpose switch use. Connected to pin X- when SEL = 1.
[1]
HWQFN56R package die supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
CBTL06122_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
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NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
7. Functional description
Refer to Figure 4 "Functional diagram". The CBTL06122 uses 3.3 V power supply. All signal paths are implemented using high-bandwidth pass-gate technology, are bidirectional and no clock or reset signal is needed for the multiplexer to function. The switch position is selected using the select signal (SEL), which can be latched using the latch enable pin (LE_N). The detailed operation is described in Section 7.1.
7.1 MUX select (SEL) function
The internal multiplexer switch position is controlled by two logic inputs SEL and LE_N as described below.
Table 3. SEL 0 1 MUX select control Dx high-impedance active; follows IN_x TXx; RXx active; follows IN_x high-impedance
The switch position select input signal SEL controls the MUX through a flow-through latch, which is gated by the latch enable input signal LE_N (active LOW). The latch is open when LE_N is LOW; in this state the internal switch position will respond to the state of the SEL input signal. The latch is closed when LE_N is HIGH, and the switch position will not respond to input state changes on the SEL input.
Table 4. LE_N 0 1 MUX select latch control Internal MUX select responds to changes on SEL latched
IN_x+
Dx+ TXx+ Dx- TXx- internal MUX select TRANSPARENT LATCH SEL LE_N
002aad088
IN_x-
Fig 7.
MUX select function
CBTL06122_2
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Product data sheet
Rev. 02 -- 16 April 2009
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NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
7.2 Shutdown function
The CBTL06122 provides a shutdown function to minimize power consumption when the application is not active but power to the CBTL06122 is provided. Pin XSD (active LOW) puts all channels in off mode (non-conducting) while reducing current consumption to near-zero.
Table 5. XSD 0 1 Shutdown function State shutdown active
8. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Tcase Vesd Parameter supply voltage case temperature electrostatic discharge voltage for operation within specification HBM CDM
[1] [2]
Conditions
Min -0.3 -40 -
Max +5 +85 4000 1000
Unit V C V V
[1] [2]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 7. Symbol VDD VI Tamb Recommended operating conditions Parameter supply voltage input voltage ambient temperature operating in free air Conditions Min 3.0 -40 Typ 3.3 Max 3.6 3.6 +85 Unit V V C
CBTL06122_2
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Product data sheet
Rev. 02 -- 16 April 2009
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CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
10. Characteristics
10.1 General characteristics
Table 8. Symbol IDD Ptot tstartup trcfg General characteristics Parameter supply current total power dissipation start-up time reconfiguration time Conditions operating mode (XSD = HIGH); VDD = 3.3 V shutdown mode (XSD = LOW); VDD = 3.3 V operating mode (XSD = HIGH); VDD = 3.3 V supply voltage valid or XSD going HIGH to channel specified operating characteristics SEL state change to channel specified operating characteristics Min Typ 0.2 Max 1 10 5 1 1 Unit mA A mW ms ms
10.2 DisplayPort channel characteristics
Table 9. Symbol VI VIC VID DDIL DisplayPort channel characteristics Parameter input voltage common-mode input voltage differential input voltage differential insertion loss channel is on; 0 Hz f 1.0 GHz channel is on; f = 2.5 GHz channel is off; 0 Hz f 3.0 GHz DDRL differential return loss channel is on; 0 Hz f 1.0 GHz adjacent channels are on; 0 Hz f 1.0 GHz -3.0 dB intercept -5.0 dB intercept tPD tsk(dif) tsk propagation delay differential skew time skew time from left-side port to right-side port or vice versa intra-pair inter-pair DDNEXT differential near-end crosstalk B bandwidth Conditions Min -0.3 0 -1.2 -2.5 -4.5 Typ -1.6 2.5 4.0 180 Max +2.6 2.0 +1.2 -20 -10 -30 5 180 Unit V V V dB dB dB dB dB GHz GHz ps ps ps
10.3 AUX and DDC ports
Table 10. Symbol VI VIC VID tPD AUX and DDC port characteristics Parameter input voltage common-mode input voltage differential input voltage propagation delay from left-side port to right-side port or vice versa
[1]
Conditions DDC or AUX DDC or AUX
Min -0.3 0 -1.2 -
Typ 180
Max +2.6 2.0 +1.2 -
Unit V V V ps
[1]
Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.
CBTL06122_2
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Product data sheet
Rev. 02 -- 16 April 2009
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CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
10.4 HPD input, HPD output
Table 11. Symbol VI tPD
[1] [2]
HPD input and output characteristics Parameter input voltage propagation delay from HPD_SINK to HPD_SOURCE Conditions
[1] [2]
Min -0.3 -
Typ 180
Max 3.6 -
Unit V ps
Low-speed input changes state on cable plug/unplug. Time from HPD_SINK changing state to HPD changing state. Includes HPD rise/fall time.
10.5 MUX select and latch input
Table 12. Symbol VIH VIL ILI SEL, LE_N input characteristics Parameter HIGH-level input voltage LOW-level input voltage input leakage current Conditions SEL/LE_N SEL/LE_N measured with input at VIH(max) and VIL(min) Min 2.0 0 Typ Max 3.6 0.8 10 Unit V V A
11. Test information
11.1 Switch test fixture requirements
The test fixture for switch S-parameter measurement shall be designed and built to specific requirements, as described below, to ensure good measurement quality and consistency.
* The test fixture shall be a FR4-based PCB of the microstrip structure; the dielectric
thickness or stack-up shall be about 4 mils.
* The total thickness of the test fixture PCB shall be 1.57 mm (0.62 in). * The measurement signals shall be launched into the switch from the top of the test
fixture, capturing the through-hole stub effect.
* Traces between the DUT and measurement ports (SMA or microprobe) should be
uncoupled from each other, as much as possible. Therefore, the traces should be routed in such a way that traces will diverge from each other exiting from the switch pin field.
* The trace lengths between the DUT and measurement port shall be minimized. The
maximum trace length shall not exceed 1000 mils. The trace lengths between the DUT and measurement port shall be equal.
* All of the traces on the test board and add-in card must be held to a characteristic
impedance of 50 with a tolerance of 7 %.
* SMA connector is recommended for ease of use. The SMA launch structure shall be
designed to minimize the connection discontinuity from SMA to the trace. The impedance range of the SMA seen from a TDR with a 60 ps rise time should be within 50 7 .
CBTL06122_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
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CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
12. Package outline
HWQFN56R: plastic thermal enhanced very very thin quad flat package; no leads; 56 terminals; resin based; body 11 x 5 x 0.7 mm
SOT1033-1
D
B
A
terminal 1 index area E A
detail X
e1 e 1/2 e L1 L
20
C v w
29
M M
b
21 28
CAB C
y1 C
y
e Eh 1/2 e
e2
1 56 49
48
Dh X 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.8 b 0.27 0.23 D 5.1 4.9 Dh 2.5 2.3 E 11.1 10.9 Eh 8.5 8.3 e 0.5 e1 3.5 e2 9.5 L 0.42 0.38 L1 0.1 0.0 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
OUTLINE VERSION SOT1033-1
REFERENCES IEC --JEDEC --JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 07-09-19 07-12-01
Fig 8.
CBTL06122_2
Package outline HWQFN56R (SOT1033-1)
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
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NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Product data sheet
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CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 9) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 and 14
Table 13. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 14. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 9.
CBTL06122_2
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Product data sheet
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CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 9.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 15. Acronym AUX CDM CMOS DDC DP DUT DVI ESD HBM HDMI HPD I/O MUX PCB PCI PCIe PEG SMA TDR
CBTL06122_2
Abbreviations Description Auxiliary channel in DisplayPort definition Charged-Device Model Complementary Metal-Oxide Semiconductor Direct Display Control DisplayPort Device Under Test Digital Video Interface ElectroStatic Discharge Human Body Model High-Definition Multimedia Interface Hot Plug Detect Input/Output Multiplexer Printed-Circuit Board Peripheral Component Interconnect PCI Express PCI Express Graphics SubMiniature, version A (connector) Time-Domain Reflectometry
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Product data sheet
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CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
15. Revision history
Table 16. Revision history Release date 20090416 Data sheet status Product data sheet Change notice Supersedes CBTL06122_1 Document ID CBTL06122_2 Modifications:
* *
Descriptive title of data sheet changed from "High-performance 4 GHz bandwidth hex display multiplexer" to "High-performance DisplayPort/PCIe Gen2 hex display multiplexer" Section 1 "General description": - 1st paragraph, 1st sentence: changed from "... and PCI Express applications." to "... and PCI Express Gen2 applications." - 1st paragraph, 2nd sentence: changed from "... PCI Express or DisplayPort signals, ..." to "... PCI Express Gen2 signals, ..." - 2nd paragraph, 1st sentence: changed from "... high-performance PCI Express and DisplayPort applications." to "... high-performance PCI Express and DisplayPort applications."
*
Section 2 "Features": - 1st bullet item: changed from "... PCI Express signals" to "... PCI Express Gen2 signals" - 13th bullet item: changed from "ESD 8 kV HBM" to "ESD 4 kV HBM"
* * *
Section 3 "Applications", 1st bullet item: changed from "... PCI Express switching/multiplexing" to "... PCI Express Gen2 switching/multiplexing" Table 6 "Limiting values", Vesd (HBM) maximum value changed from "8000 V" to "4000 V" Table 9 "DisplayPort channel characteristics": - updated DDIL values - updated DDRL values - updated DDNEXT values - updated B values
CBTL06122_1
20080523
Product data sheet
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CBTL06122_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
17 of 19
NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTL06122_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 April 2009
18 of 19
NXP Semiconductors
CBTL06122
High-performance DP/PCIe Gen2 hex display multiplexer
18. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 8 9 10 10.1 10.2 10.3 10.4 10.5 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 9 MUX select (SEL) function . . . . . . . . . . . . . . . . 9 Shutdown function . . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Recommended operating conditions. . . . . . . 10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 General characteristics . . . . . . . . . . . . . . . . . . 11 DisplayPort channel characteristics . . . . . . . . 11 AUX and DDC ports . . . . . . . . . . . . . . . . . . . . 11 HPD input, HPD output. . . . . . . . . . . . . . . . . . 12 MUX select and latch input . . . . . . . . . . . . . . . 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Switch test fixture requirements . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering of SMD packages . . . . . . . . . . . . . . 14 Introduction to soldering . . . . . . . . . . . . . . . . . 14 Wave and reflow soldering . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 April 2009 Document identifier: CBTL06122_2

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